1. Field of the Invention
The present invention relates generally to digital processing circuits, and more specifically to post-fabrication tuning techniques for logic components.
2. Brief Description of the Related Art
Process variation will greatly impact the power and performance of future microprocessors. Design approaches based on multiple supply or threshold voltage assignment provide techniques to statically tune critical path delays for energy savings. One such approach has been referred to as “clustered voltage scaling.” See K. Usami, M. Horowitz, “Clustered Voltage Scaling Technique for Low-Power Design,” Proceedings of the International Workshop on Low Power Design, pp. 3-8, April 1995 and L. Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye, V. De, “Design and optimization of dual-threshold circuits for low-voltage low-power applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 16-24, March 1999. Because clustered voltage scaling techniques are not dynamic, they cannot adapt power consumption to resource demand. Since the clustered voltage scaling systems assign different voltages at the time of design, they place higher supply voltages on circuits requiring higher performance and lower supply voltages on circuits requiring only lower performance. Further, under process variation, delay of critical paths may vary, and the large number of critical paths in circuits can reduce the maximum operating frequency of pipelined processors. See K. A. Bowman, Steven G. Duvall, and J. D. Meindl, “Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration,” IEEE Journal of Solid-State Circuits, pp. 183-190, February 2002.
One proposed post-fabrication solution is to adaptively tune the back-body bias to combat variations for logic structures. J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage,” in IEEE ISSCC Dig. Tech. Papers, pp. 422-423, February 2002. Dual-voltage operation has also been proposed to enable robust memory operation under variations. J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, F. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, D. Wendel, “Implementation of the CELL Broadband Engine in a 65 nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6 GHz at 1.3V,” in ISSCC 2007 Dig. Tech Papers, pp. 322-323, February 2007.
Another approach was disclosed in U.S. Patent Application Publication US2005/0253462, entitled “Integrated Circuit with Multiple Power Domains” and filed on Feb. 7, 2005. Additionally, in U.S. Patent Application Publication No. US2007/0200593, entitled “Digital Circuit with Dynamic Power and Performance Control via Per-Block Selectable Operating Voltage” and filed on Dec. 13, 2005, a digital circuit with dynamic power and performance control via per-block selectable operating voltage level is proposed to permit dynamic tailoring of operating power to processing demand and/or compensation for processing variation.